QEMU源码全解析 —— virtio（16）

已于 2024-02-06 14:51:45 修改
阅读量607 收藏 8
点赞数 11
分类专栏： QEMU/KVM KVM 文章标签： QEMU KVM virtio
于 2023-12-19 11:20:32 首次发布
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接： https://blog.csdn.net/phmatthaus/article/details/135078084
版权
QEMU/KVM 同时被 2 个专栏收录
123 篇文章 36 订阅 ¥49.90 ¥99.00
已订阅 8折续费
KVM
88 篇文章 19 订阅
订阅专栏
您已是超级会员，正在免费阅读会员专享内容
查看更多超级会员权益
本文详细介绍了QEMU中virtio_pci_device_plugged函数的工作流程，包括调用pci_register_bar注册内存区域，使用msix_init_exclusive_bar处理MSI中断，以及设置PCI配置空间的读写函数。这些步骤构成了QEMU为virtio balloon设备准备的基础。通过图表展示了virtio PCI代理设备与virtio设备的继承关系以及初始化过程中的关键函数。
摘要由CSDN通过智能技术生成

接前一篇文章：

上一回讲解了virtio_pci_device_plugged函数的第二部分的前两小部分，本回继续讲解virtio_pci_device_plugged函数的其余部分。为了便于理解，再次贴出virtio_pci_device_plugged函数源码，在hw/ virtio /virtio-pci.c中，如下： 

  1. /* This is called by virtio-bus just after the device is plugged. */
  2. static void virtio_pci_device_plugged(DeviceState *d, Error **errp)
  3. {
  4.     VirtIOPCIProxy *proxy = VIRTIO_PCI(d);
  5.     VirtioBusState *bus = &proxy->bus;
  6.     bool legacy = virtio_pci_legacy(proxy);
  7.     bool modern;
  8.     bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY;
  9.     uint8_t *config;
  10.     uint32_t size;
  11.     VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus);
  12.  
  13.     /*
  14.      * Virtio capabilities present without
  15.      * VIRTIO_F_VERSION_1 confuses guests
  16.      */
  17.     if (!proxy->ignore_backend_features &&
  18.             !virtio_has_feature(vdev->host_features, VIRTIO_F_VERSION_1)) {
  19.         virtio_pci_disable_modern(proxy);
  20.  
  21.         if (!legacy) {
  22.             error_setg(errp, "Device doesn't support modern mode, and legacy"
  23.                              " mode is disabled");
  24.             error_append_hint(errp, "Set disable-legacy to off\n");
  25.  
  26.             return;
  27.         }
  28.     }
  29.  
  30.     modern = virtio_pci_modern(proxy);
  31.  
  32.     config = proxy->pci_dev.config;
  33.     if (proxy->class_code) {
  34.         pci_config_set_class(config, proxy->class_code);
  35.     }
  36.  
  37.     if (legacy) {
  38.         if (!virtio_legacy_allowed(vdev)) {
  39.             /*
  40.              * To avoid migration issues, we allow legacy mode when legacy
  41.              * check is disabled in the old machine types (< 5.1).
  42.              */
  43.             if (virtio_legacy_check_disabled(vdev)) {
  44.                 warn_report("device is modern-only, but for backward "
  45.                             "compatibility legacy is allowed");
  46.             } else {
  47.                 error_setg(errp,
  48.                            "device is modern-only, use disable-legacy=on");
  49.                 return;
  50.             }
  51.         }
  52.         if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) {
  53.             error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by"
  54.                        " neither legacy nor transitional device");
  55.             return;
  56.         }
  57.         /*
  58.          * Legacy and transitional devices use specific subsystem IDs.
  59.          * Note that the subsystem vendor ID (config + PCI_SUBSYSTEM_VENDOR_ID)
  60.          * is set to PCI_SUBVENDOR_ID_REDHAT_QUMRANET by default.
  61.          */
  62.         pci_set_word(config + PCI_SUBSYSTEM_ID, virtio_bus_get_vdev_id(bus));
  63.         if (proxy->trans_devid) {
  64.             pci_config_set_device_id(config, proxy->trans_devid);
  65.         }
  66.     } else {
  67.         /* pure virtio-1.0 */
  68.         pci_set_word(config + PCI_VENDOR_ID,
  69.                      PCI_VENDOR_ID_REDHAT_QUMRANET);
  70.         pci_set_word(config + PCI_DEVICE_ID,
  71.                      PCI_DEVICE_ID_VIRTIO_10_BASE + virtio_bus_get_vdev_id(bus));
  72.         pci_config_set_revision(config, 1);
  73.     }
  74.     config[PCI_INTERRUPT_PIN] = 1;
  75.  
  76.  
  77.     if (modern) {
  78.         struct virtio_pci_cap cap = {
  79.             .cap_len = sizeof cap,
  80.         };
  81.         struct virtio_pci_notify_cap notify = {
  82.             .cap.cap_len = sizeof notify,
  83.             .notify_off_multiplier =
  84.                 cpu_to_le32(virtio_pci_queue_mem_mult(proxy)),
  85.         };
  86.         struct virtio_pci_cfg_cap cfg = {
  87.             .cap.cap_len = sizeof cfg,
  88.             .cap.cfg_type = VIRTIO_PCI_CAP_PCI_CFG,
  89.         };
  90.         struct virtio_pci_notify_cap notify_pio = {
  91.             .cap.cap_len = sizeof notify,
  92.             .notify_off_multiplier = cpu_to_le32(0x0),
  93.         };
  94.  
  95.         struct virtio_pci_cfg_cap *cfg_mask;
  96.  
  97.         virtio_pci_modern_regions_init(proxy, vdev->name);
  98.  
  99.         virtio_pci_modern_mem_region_map(proxy, &proxy->common, &cap);
  100.         virtio_pci_modern_mem_region_map(proxy, &proxy->isr, &cap);
  101.         virtio_pci_modern_mem_region_map(proxy, &proxy->device, &cap);
  102.         virtio_pci_modern_mem_region_map(proxy, &proxy->notify, &notify.cap);
  103.  
  104.         if (modern_pio) {
  105.             memory_region_init(&proxy->io_bar, OBJECT(proxy),
  106.                                "virtio-pci-io", 0x4);
  107.  
  108.             pci_register_bar(&proxy->pci_dev, proxy->modern_io_bar_idx,
  109.                              PCI_BASE_ADDRESS_SPACE_IO, &proxy->io_bar);
  110.  
  111.             virtio_pci_modern_io_region_map(proxy, &proxy->notify_pio,
  112.                                             &notify_pio.cap);
  113.         }
  114.  
  115.         pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
  116.                          PCI_BASE_ADDRESS_SPACE_MEMORY |
  117.                          PCI_BASE_ADDRESS_MEM_PREFETCH |
  118.                          PCI_BASE_ADDRESS_MEM_TYPE_64,
  119.                          &proxy->modern_bar);
  120.  
  121.         proxy->config_cap = virtio_pci_add_mem_cap(proxy, &cfg.cap);
  122.         cfg_mask = (void *)(proxy->pci_dev.wmask + proxy->config_cap);
  123.         pci_set_byte(&cfg_mask->cap.bar, ~0x0);
  124.         pci_set_long((uint8_t *)&cfg_mask->cap.offset, ~0x0);
  125.         pci_set_long((uint8_t *)&cfg_mask->cap.length, ~0x0);
  126.         pci_set_long(cfg_mask->pci_cfg_data, ~0x0);
  127.     }
  128.  
  129.     if (proxy->nvectors) {
  130.         int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
  131.                                           proxy->msix_bar_idx, NULL);
  132.         if (err) {
  133.             /* Notice when a system that supports MSIx can't initialize it */
  134.             if (err != -ENOTSUP) {
  135.                 warn_report("unable to init msix vectors to %" PRIu32,
  136.                             proxy->nvectors);
  137.             }
  138.             proxy->nvectors = 0;
  139.         }
  140.     }
  141.  
  142.     proxy->pci_dev.config_write = virtio_write_config;
  143.     proxy->pci_dev.config_read = virtio_read_config;
  144.  
  145.     if (legacy) {
  146.         size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev)
  147.             + virtio_bus_get_vdev_config_len(bus);
  148.         size = pow2ceil(size);
  149.  
  150.         memory_region_init_io(&proxy->bar, OBJECT(proxy),
  151.                               &virtio_pci_config_ops,
  152.                               proxy, "virtio-pci", size);
  153.  
  154.         pci_register_bar(&proxy->pci_dev, proxy->legacy_io_bar_idx,
  155.                          PCI_BASE_ADDRESS_SPACE_IO, &proxy->bar);
  156.     }
  157. }

（2.3）virtio_pci_device_plugged函数接着调用pci_register_bar函数，将VirtIOPCIProxy的modern_bar这一MemoryRegion注册到系统中。代码片段如下： 

  1.         pci_register_bar(&proxy->pci_dev, proxy->modern_mem_bar_idx,
  2.                          PCI_BASE_ADDRESS_SPACE_MEMORY |
  3.                          PCI_BASE_ADDRESS_MEM_PREFETCH |
  4.                          PCI_BASE_ADDRESS_MEM_TYPE_64,
  5.                          &proxy->modern_bar);

pci_register_bar函数在hw/ pci /pci.c中，代码如下： 

  1. void pci_register_bar(PCIDevice *pci_dev, int region_num,
  2.                       uint8_t type, MemoryRegion *memory)
  3. {
  4.     PCIIORegion *r;
  5.     uint32_t addr; /* offset in pci config space */
  6.     uint64_t wmask;
  7.     pcibus_t size = memory_region_size(memory);
  8.     uint8_t hdr_type;
  9.  
  10.     assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */
  11.     assert(region_num >= 0);
  12.     assert(region_num < PCI_NUM_REGIONS);
  13.     assert(is_power_of_2(size));
  14.  
  15.     /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
  16.     hdr_type =
  17.         pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
  18.     assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2);
  19.  
  20.     r = &pci_dev->io_regions[region_num];
  21.     r->addr = PCI_BAR_UNMAPPED;
  22.     r->size = size;
  23.     r->type = type;
  24.     r->memory = memory;
  25.     r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
  26.                         ? pci_get_bus(pci_dev)->address_space_io
  27.                         : pci_get_bus(pci_dev)->address_space_mem;
  28.  
  29.     wmask = ~(size - 1);
  30.     if (region_num == PCI_ROM_SLOT) {
  31.         /* ROM enable bit is writable */
  32.         wmask |= PCI_ROM_ADDRESS_ENABLE;
  33.     }
  34.  
  35.     addr = pci_bar(pci_dev, region_num);
  36.     pci_set_long(pci_dev->config + addr, type);
  37.  
  38.     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
  39.         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
  40.         pci_set_quad(pci_dev->wmask + addr, wmask);
  41.         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
  42.     } else {
  43.         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
  44.         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
  45.     }
  46. }

（3）接下来，调用msix_init_exclusive_bar函数注册与 msi 中断有关的数据。代码片段如下： 

  1.    if (proxy->nvectors) {
  2.         int err = msix_init_exclusive_bar(&proxy->pci_dev, proxy->nvectors,
  3.                                           proxy->msix_bar_idx, NULL);
  4.         if (err) {
  5.             /* Notice when a system that supports MSIx can't initialize it */
  6.             if (err != -ENOTSUP) {
  7.                 warn_report("unable to init msix vectors to %" PRIu32,
  8.                             proxy->nvectors);
  9.             }
  10.             proxy->nvectors = 0;
  11.         }
  12.     }

msix_init_exclusive_bar函数在hw/pci/msix.c中，代码如下： 

  1. int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
  2.                             uint8_t bar_nr, Error **errp)
  3. {
  4.     int ret;
  5.     char *name;
  6.     uint32_t bar_size = 4096;
  7.     uint32_t bar_pba_offset = bar_size / 2;
  8.     uint32_t bar_pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
  9.  
  10.     /*
  11.      * Migration compatibility dictates that this remains a 4k
  12.      * BAR with the vector table in the lower half and PBA in
  13.      * the upper half for nentries which is lower or equal to 128.
  14.      * No need to care about using more than 65 entries for legacy
  15.      * machine types who has at most 64 queues.
  16.      */
  17.     if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
  18.         bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
  19.     }
  20.  
  21.     if (bar_pba_offset + bar_pba_size > 4096) {
  22.         bar_size = bar_pba_offset + bar_pba_size;
  23.     }
  24.  
  25.     bar_size = pow2ceil(bar_size);
  26.  
  27.     name = g_strdup_printf("%s-msix", dev->name);
  28.     memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);
  29.     g_free(name);
  30.  
  31.     ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
  32.                     0, &dev->msix_exclusive_bar,
  33.                     bar_nr, bar_pba_offset,
  34.                     0, errp);
  35.     if (ret) {
  36.         return ret;
  37.     }
  38.  
  39.     pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
  40.                      &dev->msix_exclusive_bar);
  41.  
  42.     return 0;
  43. }

（4）virtio_pci_device_plugged函数还会将VirtPCIProxy设备PCI配置空间的读写函数分别设置成virtio_write_config和virtio_read_config。代码片段如下： 

  1.     proxy->pci_dev.config_write = virtio_write_config;
  2.     proxy->pci_dev.config_read = virtio_read_config;

virtio_pci_device_plugged函数经过一系列的函数调用，就在QEMU侧准备好了virtio balloon设备。其它设备与此类似。

通过图来整体总结一下：

  • virtio PCI代理设备与virtio设备的相关类型的继承关系如下图所示：

  • virtio设备初始化过程中涉及的相关函数及其所对应的类型如下图所示：

预知后事如何，且看下回分解。

举报

选择你想要举报的内容（必选）
  • 内容涉黄
  • 政治相关
  • 内容抄袭
  • 涉嫌广告
  • 内容侵权
  • 侮辱谩骂
  • 样式问题
  • 其他

取消

确定